1. Field of the Invention
The invention relates to a lateral transistor from which a metal layer and/or a semiconductor region at one of the corners of a collector region surrounding an emitter region are/is removed and a metal layer for drawing a current from the emitter is disposed at the corner.
2. Description of the Prior Art
FIGS. 7A and 7B show a conventional single-element lateral transistor. The configuration of FIGS. 7A and 7B comprises an n-type semiconductor layer 1, a collector region 2, namely a p-type semiconductor region in the n-type semiconductor layer 1, an emitter 3, namely a p-type semiconductor region in the n-type semiconductor layer 1, an insulating layer 4 that covers the surface of the n-type semiconductor layer 1, a collector electrode 5 on the surface of the insulating layer 4 and extending through a hole penetrating through the insulating layer 4, an insulating layer 6 that covers the insulating layer 4 and the collector electrode 5, and an emitter electrode 7 extending from the emitter region 3.
In this conventional lateral transistor, an n-type base region is disposed between the periphery of the emitter region 3 and the square, doughnut-shaped collector region 2 that surrounds the emitter region 3. The transistor includes the collector region 2, the n-type semiconductor layer 1, and the emitter region 3. Such a lateral transistor requires an electrode extending from the central emitter region 3. In the conventional transistor, a middle portion of the square collector electrode 5 is removed and an emitter electrode 7 is located along the removed portion.
FIGS. 8A and 8B show another conventional single-element lateral transistor. Explanation of the elements of FIGS. 8A and 8B is omitted because the same numerals as in FIGS. 7A and 7B denote the same elements or components. In the lateral transistor shown in FIGS. 8A and 8B, an n-type base region is disposed between the periphery of emitter region 3 and the square, doughnut-shaped collector region 2 that surrounds the emitter region 3. Further, in such a lateral transistor, a metal layer 7 extends through a penetrating hole in both the insulating layer 4 and the overlying insulating layer 6 without removal of the metal 5 at any sides of the square collector electrode 5. This metal layer 7 is disposed on insulating layer 6 as an emitter electrode.
FIGS. 9A and 9B show another lateral transistor wherein a plurality of prior art elements constitute a unit transistor, and the unit transistors are connected in parallel. The conventional lateral transistor shown in FIGS. 9A and 9B includes a plurality of lattice-shaped transistor cells. In each transistor cell, an n-type base region is disposed between the periphery of emitter region 3 and the square, doughnut-shaped collector region 2 surrounding the emitter region 3. The collector region 2, the n-type base region, and the emitter region 3 constitute a transistor. Connecting a plurality of unit transistors in parallel increases power handling capacity.
In order to connect the plurality of unit transistors, the metal layer 7 is disposed in penetrating holes opened in the both insulating layer 4 and the overlying insulating layer 6 without removing metal portions at each side of the square collector electrode 5, as FIGS. 9A and 9B show. The emitters in each transistor cell are connected via this metal layer 7.
FIGS. 10A and 10B show a lateral transistor wherein a unit transistor includes a plurality of elements of the prior art, and the unit transistors are connected in parallel. In the structures of FIGS. 10A and 10B, it is possible simply to open penetrating holes in both the insulating layer 4 and the insulating layer 6 which overlay the emitter region 3 and to connect the emitter regions 3 of a plurality of transistor cells mutually by multi-layer interconnections through these penetrating holes.
However, in the conventional lateral transistor shown in FIGS. 7A and 7B, a metal portion in one side of the collector electrode 5 is removed so the emitter electrode 7 can extend along that portion. If that portion of collector electrode 5 is removed, the operational area of the lateral transistor is reduced because the transistor operates mainly at the periphery of the central emitter region 3 and the surrounding collector region 2. Accordingly, in this configuration, a power transistor cannot achieve sufficiently large power capacity.
The conventional lateral transistor shown in FIGS. 8A and 8B includes the insulating layer 6 over the collector electrode 5 without removal of a metal portion at one side of the collector electrode 5. The emitter electrode 7 is drawn out on the top surface of the insulating layer 6 through a penetrating hole opened in the insulating layer 4 and the overlying insulating layer 6. Although the current capacity per transistor cell is enlarged, since the collector electrode 5 can be drawn out from each of the four sides of the collector region 2 in the transistor cell, additional process steps are required to open the penetrating holes in the insulating layer 6. Moreover, the dimensions of the emitter must be enlarged. Accordingly, such a transistor is less advantageous in reducing the size of the transistor.
The conventional lateral transistor shown in FIGS. 9A and 9B includes the insulating layer 6 over the collector electrode 5 without removal of a metal portion at one side of the collector electrode 5. The emitter electrode 7 is drawn out on the top surface of the insulating layer 6 through penetrating holes opened in insulating layer 4 and the overlying insulating layer 6, mutually connecting each emitter in each transistor cell. In this configuration, the current capacity per transistor cell is enlarged because the collector electrode 5 can be drawn out from each of the four sides of collector region 2 in the transistor cell. However, the opening in the insulating layer 4 and the overlying insulating layer 6 must be enlarged because it is difficult to contact a diffused region with aluminum when electrodes are drawn out from the diffused region. For this reason, the dimensions of the emitters must also be enlarged. Accordingly, such a transistor is less advantageous in reducing the size of the transistor.
Further, in the configuration of FIGS. 10A and 10B, each transistor cell is inevitably large because the dimension of the emitter is enlarged. Accordingly, such a transistor is less advantageous in shrinking the size of a chip.